In many device applications, it is desired to short the source (or drain, or both) of a FET (field effect transistor) to the gate. The conventional method of making a gate-to-source contact requires contact holes to be opened in the first dielectric layer and the actual metal connection to be made between the source (or drain) and the gate with another layer of interconnection metal. Such a metal connection is routed around the active region of the device.
Nakayama et al in U.S. Pat. No. 4,628,338 disclose a semiconductor device in which a gate metal is contacted with an ohmic contact to a source or drain region. However, the contact is not direct, but rather is made through an extension of the gate electrode, thereby requiring undue space. Additionally, the metallization Nakayama specifies is not easily adapted to dense, high yielding circuits. More specifically, the minimum thickness of ohmic contact metal necessary to achieve a consistent contact is not compatible with the lift-off patterning technique necessary to define the metal.
Sugimoto Japanese patent 59-18676 discloses a direct shorting contact device which uses minimal space, and exhibits high yielding characteristics in dense circuits. This contact is built with silicon wafer processing, and the materials and processing steps used are incompatible with GaAs devices. No combination of the materials or structures in Nakayama and Sugimoto's disclosures may be used for high yielding, densely packed circuits on III-V semiconductors, so a different metallization scheme must be found to achieve this direct shorting contact.